![digital logic - In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth? - digital logic - In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth? -](https://i.stack.imgur.com/UCOWS.gif)
digital logic - In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth? -
![digital logic - is it possible to make asynchronous down counter modulo 6 with 3 JK flip-flop? - Electrical Engineering Stack Exchange digital logic - is it possible to make asynchronous down counter modulo 6 with 3 JK flip-flop? - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/DrYjD.png)
digital logic - is it possible to make asynchronous down counter modulo 6 with 3 JK flip-flop? - Electrical Engineering Stack Exchange
![In the modulo 6 ripple counter shown in the figure. the output of the 2 input gate is used to clear the J K flip flops.The 2 input gate is In the modulo 6 ripple counter shown in the figure. the output of the 2 input gate is used to clear the J K flip flops.The 2 input gate is](https://df0b18phdhzpx.cloudfront.net/ckeditor_assets/pictures/1594855/original_5.23-28.png)